[Resource Topic] 2024/1988: Garbled Circuits with 1 Bit per Gate

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Title:
Garbled Circuits with 1 Bit per Gate

Authors: Hanlin Liu, Xiao Wang, Kang Yang, Yu Yu

Abstract:

We present a garbling scheme for Boolean circuits with 1 bit per gate communication based on either ring learning with errors (RLWE) or NTRU assumption, with key-dependent message security. The garbling consists of 1) a homomorphically encrypted seed that can be expanded to encryption of many pseudo-random bits and 2) one-bit stitching information per gate to reconstruct garbled tables from the expanded ciphertexts. By using low-complexity PRGs, both the garbling and evaluation of each gate require only O(1) homomorphic addition/multiplication operations without bootstrapping.

ePrint: https://eprint.iacr.org/2024/1988

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