[Resource Topic] 2024/1817: Improved ML-DSA Hardware Implementation With First Order Masking Countermeasure

Welcome to the resource topic for 2024/1817

Title:
Improved ML-DSA Hardware Implementation With First Order Masking Countermeasure

Authors: Kamal Raj, Prasanna Ravi, Tee Kiah Chia, Anupam Chattopadhyay

Abstract:

We present the protected hardware implementation of the Module-Lattice-Based Digital Signature Standard (MLDSA). ML-DSA is an extension of Dilithium 3.1, which is the winner of the Post Quantum Cryptography (PQC) competition in the digital signature category. The proposed design is based on the existing high-performance Dilithium 3.1 design. We implemented existing Dilithium masking gadgets in hardware, which were only implemented in software. The masking gadgets are integrated with the unprotected ML-DSA design and functional verification of the complete design is verified with the Known Answer Tests(KATs) generated from an updated ML-DSA software implementation. We also present the practical power side-channel attack experimental results by implementing masking gadgets on the standard sidechannel evaluation FPGA board and collecting power traces up-to 1 million traces. The proposed protected design has the overhead of 1.127× LUT, 1.2× Flip-Flop, and 378× execution time compared to unprotected design. The experimental results show that it resists side-channel attacks.

ePrint: https://eprint.iacr.org/2024/1817

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