[Resource Topic] 2024/1367: A Better Kyber Butterfly for FPGAs

Welcome to the resource topic for 2024/1367

Title:
A Better Kyber Butterfly for FPGAs

Authors: Jonas Bertels, Quinten Norga, Ingrid Verbauwhede

Abstract:

Kyber was selected by NIST as a Post-Quantum
Cryptography Key Encapsulation Mechanism standard. This
means that the industry now needs to transition and adopt
these new standards. One of the most demanding operations in
Kyber is the modular arithmetic, making it a suitable target for
optimization. This work offers a novel modular reduction design
with the lowest area on Xilinx FPGA platforms. This novel design,
through K-reduction and LUT-based reduction, utilizes 49 LUTs
and 1 DSP as opposed to Xing and Li’s 2021 CHES design
requiring 90 LUTs and 1 DSP for one modular multiplication.
Our design is the smallest modular multiplier reported as of
today.

ePrint: https://eprint.iacr.org/2024/1367

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