[Resource Topic] 2023/1749: Dora: Processor Expressiveness is (Nearly) Free in Zero-Knowledge for RAM Programs

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Dora: Processor Expressiveness is (Nearly) Free in Zero-Knowledge for RAM Programs

Authors: Aarushi Goel, Mathias Hall-Andersen, Gabriel Kaptchuk


Existing protocols for proving the correct execution of a RAM program in zero-knowledge are plagued by a processor expressiveness trade-off : supporting fewer instructions results in smaller processor circuits (which improves performance), but may result in more program execution steps because non-supported instruction must be emulated over multiple processor steps (which diminishes performance).

We present Dora, a concretely efficient zero-knowledge protocol for RAM programs that sidesteps this tension by making it (nearly) free to add additional instructions to the processor. The computational and communication complexity of proving each step of a computation in Dora, is constant in the number of supported instructions. Dora is also highly generic and only assumes the existence of linearly homomorphic commitments. We implement Dora and demonstrate that on commodity hardware it can prove the correct execution of a processor with thousands of instruction, each of which has thousands of gates, in just a few milliseconds per step.

ePrint: https://eprint.iacr.org/2023/1749

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