[Resource Topic] 2021/493: Optimizing BIKE for the Intel Haswell and ARM Cortex-M4

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Title:
Optimizing BIKE for the Intel Haswell and ARM Cortex-M4

Authors: Ming-Shing Chen, Tung Chou, Markus Krausz

Abstract:

BIKE is a key encapsulation mechanism that entered the third round of the NIST post-quantum cryptography standardization process. This paper presents two constant-time implementations for BIKE, one tailored for the Intel Haswell and one tailored for the ARM Cortex-M4. Our Haswell implementation is much faster than the avx2 implementation written by the BIKE team: for bikel1, the level-1 parameter set, we achieve a 1.39x speedup for decapsulation (which is the slowest operation) and a 1.33x speedup for the sum of all operations. For bikel3, the level-3 parameter set, we achieve a 1.5x speedup for decapsulation and a 1.46x speedup for the sum of all operations. Our M4 implementation is more than two times faster than the non-constant-time implementation portable written by the BIKE team. The speedups are achieved by both algorithm-level and instruction-level optimizations.

ePrint: https://eprint.iacr.org/2021/493

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