[Resource Topic] 2018/943: Valiant's Universal Circuits Revisited: an Overall Improvement and a Lower Bound

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Valiant’s Universal Circuits Revisited: an Overall Improvement and a Lower Bound

Authors: Shuoyao Zhao, Yu Yu, Jiang Zhang, Hanlin Liu


A universal circuit (UC) is a general-purpose circuit that can simulate arbitrary circuits (up to a certain size n). At STOC 1976 Valiant presented a graph theoretic approach to the construction of UCs, where a UC is represented by an edge universal graph (EUG) and is recursively constructed using a dedicated graph object (referred to as supernode). As a main end result, Valiant constructed a 4-way supernode of size 19 and an EUG of size 4.75n\log n (omitting smaller terms), which remained the most size-efficient even to this day (after more than 4 decades). Motivated by the emerging applications of UCs in various privacy preserving computation scenarios, we revisit Valiant’s universal circuits, and propose a size-optimal 4-way supernode of size 18, and an EUG of size 4.5n\log n. As confirmed by our implementations, we reduce the size of universal circuits (and the number of AND gates) by more than 5% in general (rather than just for small-size circuits in particular), and thus improve upon the efficiency of UC-based cryptographic applications accordingly. Our approach to the design of optimal supernodes is computer aided (rather than by hand as in previous works), which might be of independent interests. As a complement, we give lower bounds on the size of EUGs and UCs in Valiant’s framework, which significantly improves upon the generic lower bound on UC size and therefore reduces the gap between theory and practice of universal circuits.

ePrint: https://eprint.iacr.org/2018/943

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