[Resource Topic] 2018/1088: High-speed Side-channel-protected Encryption and Authentication in Hardware

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High-speed Side-channel-protected Encryption and Authentication in Hardware

Authors: Nele Mentens, Vojtech Miskovsky, Martin Novotny, Jo Vliegen


This paper describes two FPGA implementations for the encryption and authentication of data, based on the AES algorithm running in Galois/Counter mode (AES-GCM). Both architectures are protected against side-channel analysis attacks through the use of a threshold implementation (TI). The first architecture is fully unrolled and optimized for throughput. The second architecture uses a round-based structure, fits on a relatively small FPGA board, and is evaluated for side-channel attack resistance. We perform a Test Vector Leakage Assessment (TVLA), which shows no first-order leakage in the power consumption of the FPGA. To the best of our knowledge, our work is (1) the first to describe a throughput-optimized FPGA architecture of AES-GCM, protected against first-order side-channel information leakage, and (2) the first to evaluate the side-channel attack resistance of a TI-protected AES-GCM implementation.

ePrint: https://eprint.iacr.org/2018/1088

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