[Resource Topic] 2017/459: Security Analysis of Arbiter PUF and Its Lightweight Compositions Under Predictability Test

Welcome to the resource topic for 2017/459

Title:
Security Analysis of Arbiter PUF and Its Lightweight Compositions Under Predictability Test

Authors: Phuong Ha Nguyen, Durga Prasad Sahoo, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay

Abstract:

Unpredictability is an important security property of Physically Unclonable Function (PUF) in the context of statistical attacks, where the correlation between challenge-response pairs is explicitly exploited. In existing literature on PUFs, Hamming Distance test, denoted by \mathrm{HDT}(t), was proposed to evaluate the unpredictability of PUFs, which is a simplified case of the Propagation Criterion test \mathrm{PC}(t). The objective of these testing schemes is to estimate the output transition probability when there are t or less than t bits flips, and ideally, this probability value should be 0.5. In this work, we show that aforementioned two testing schemes are not enough to ensure the unpredictability of a PUF design. We propose a new test which is denoted as \mathrm{HDT}(\mathbf{e},t). This testing scheme is a fine-tuned version of the previous schemes, as it considers the flipping bit pattern vector \mathbf{e} along with parameter t. As a contribution, we provide a comprehensive discussion and analytic interpretation of \mathrm{HDT}(t), \mathrm{PC}(t) and \mathrm{HDT}(\mathbf{e},t) test schemes for Arbiter PUF (APUF), XOR PUF and Lightweight Secure PUF (LSPUF). Our analysis establishes that \mathrm{HDT}(\mathbf{e},t) test is more general in comparison with \mathrm{HDT}(t) and \mathrm{PC}(t) tests. In addition, we demonstrate a few scenarios where the adversary can exploit the information obtained from the analysis of \mathrm{HDT}(\mathbf{e},t) properties of APUF, XOR PUF and LSPUF to develop statistical attacks on them, if the ideal value of \mathrm{HDT}(\mathbf{e},t)=0.5 is not achieved for a given PUF. We validate our theoretical observations using the simulated and FPGA implemented APUF, XOR PUF and LSPUF designs.

ePrint: https://eprint.iacr.org/2017/459

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