Welcome to the resource topic for 2015/786
Title:
Buying AES Design Resistance with Speed and Energy
Authors: Jean-Michel Cioranesco, Roman Korkikian, David Naccache, Rodrigo Portella do Canto
Abstract:Fault and power attacks are two common ways of extracting secrets from tamper-resistant chips. Although several protections have been proposed to thwart these attacks, resistant designs usually claim significant area or speed overheads. Furthermore, circuit-level countermeasures are usually not reconfigurable at runtime. This paper exploits the AES’ algorithmic features to propose low-cost and low-latency protections. We provide Verilog and FPGA implementation details. Using our design, real-life applications can be configured during runtime to meet the user’s needs and the system’s constraints.
ePrint: https://eprint.iacr.org/2015/786
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