[Resource Topic] 2011/670: SHA-3 on ARM11 processors

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SHA-3 on ARM11 processors

Authors: Peter Schwabe, Bo-Yin Yang, Shang-Yi Yang


This paper presents high-speed assembly implementations of the 256-bit-output versions of all five SHA-3 finalists and of SHA-256 for the ARM11 family of processors. We report new speed records for all of the six implemented functions. For example our implementation of the round-3 version of JH-256 is 35% faster than the fastest implementation of the round-2 version of JH-256 in eBASH. Scaled with the number of rounds this is more than a 45% improvement.We also improve upon previous assembly implementations for 32-bit ARM processors. For example the implementation of Groestl-256 described in this paper is about 20% faster than the arm32 implementation in eBASH.

ePrint: https://eprint.iacr.org/2011/670

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