[Resource Topic] 2010/292: A Low-Area yet Performant FPGA Implementation of Shabal

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A Low-Area yet Performant FPGA Implementation of Shabal

Authors: Jérémie Detrey, Pierrick Gaudry, Karim Khalfallah


In this paper, we present an efficient FPGA implementation of the SHA-3 hash function candidate Shabal. Targeted at the recent Xilinx Virtex-5 FPGA family, our design achieves a relatively high throughput of 2 Gbit/s at a cost of only 153 slices, yielding a throughput-vs.-area ratio of 13.4 Mbit/s per slice. Our work can also be ported to Xilinx Spartan-3 FPGAs, on which it supports a throughput of 800 Mbit/s for only 499 slices, or equivalently 1.6 Mbit/s per slice. According to the SHA-3 Zoo website, this work is among the smallest reported FPGA implementations of SHA-3 candidates, and ranks first in terms of throughput per area.

ePrint: https://eprint.iacr.org/2010/292

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