Welcome to the resource topic for 2009/603
Title:
An FPGA Technologies Area Examination of the SHA-3 Hash Candidate Implementations
Authors: Brian Baldwin, William P. Marnane
Abstract:This paper presents an examination of the different FPGA architectures used to implement the various hash function candidates for the currently ongoing NIST-organised SHA-3 competition~\cite{Sha3NIST}. This paper is meant to be used as both a quick reference guide used in conjunction with the results table~\cite{Sha3zoo} as an aid in finding the ”best-fit” FPGA for a particular algorithm, as well as a helpful guide for explaining the many different terms and measurement units used in the various FPGA packages.
ePrint: https://eprint.iacr.org/2009/603
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