Welcome to the resource topic for 2004/187
Title:
Parallel FPGA Implementation of RSA with Residue Number Systems - Can side-channel threats be avoided? - Extended version
Authors: Mathieu Ciet, Michael Neve, Eric Peeters, Jean-Jacques Quisquater
Abstract:In this paper, we present a new parallel architecture to avoid
side-channel analyses such as: timing attack, simple/differential
power analysis, fault induction attack and simple/differential
electromagnetic analysis. We use a Montgomery Multiplication based
on Residue Number Systems. Thanks to RNS, we develop a design able
to perform an RSA signature in parallel on a set of identical and
independent coprocessors. Of independent interest, we propose a
new DPA countermeasure in the framework of RNS. It is only
(slightly) memory consuming (1.5 KBytes). Finally, we synthesized
our new architecture on FPGA and it presents promising performance
results. Even if our aim is to sketch a secure architecture, the
RSA signature is performed in less than 160 ms, with competitive
hardware resources. To our knowledge, this is the first proposal
of an architecture counteracting electromagnetic analysis apart
from hardware countermeasures reducing electromagnetic radiations.
ePrint: https://eprint.iacr.org/2004/187
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